Exemplary embodiments of the present invention relate to a semiconductor device designing technology, and more particularly, to a column path control of a semiconductor memory device.
As lines and cells constituting a semiconductor memory device get smaller, a power supply voltage thereof is lowered as well. Therefore, a semiconductor memory device that may operate in a low-voltage environment is being developed.
FIG. 1 is a block diagram showing a column path, or read path, of a conventional Dynamic Random Access Memory (DRAM) device.
Referring to FIG. 1, a read path of the DRAM device includes a pair of bit lines BL and BLb, a bit line sense amplifier (BLSA), a bus switch (SW), and a main sense amplifier (IOSA). The bit line pair BL and BLb is coupled with a memory cell C and loaded with a charge corresponding to a data of the memory cell C. The charge loaded on the bit line pair BL and BLB is sensed and amplified, and the bit line sense amplifier transfers the amplified data to a segment data bus SIO and SIOb when a column selection signal Yi is enabled. The bus switch transfers the data loaded on the segment data bus SIO and SIOb to a local data bus LIO and LIOb. The main sense amplifier senses and amplifies the data loaded on the local data bus LIO and LIOb and transfers the amplified data to a global data bus GIO.
When a selected word line WL is activated based on a row address, charges stored in the capacitors of a plurality of memory cells C coupled with the selected word line WL are loaded on the bit line pair BL and BLb. The bit line sense amplifier senses a delicate voltage difference between the bit line pair BL and BLb occurring due to the loaded charges and amplifies the delicate voltage difference.
Meanwhile, the amplified data produced by the bit line sense amplifier is transferred to the segment data bus SIO and SIOb in response to the column selection signal Yi, and the bus switch transfers the data loaded on the segment data bus SIO and SIOb to the local data bus LIO and LIOb. Then, the main sense amplifier senses and amplifies the data and transfers the amplified data to the global data bus GIO.
FIG. 2 is a circuit diagram of a conventional bus switch. Referring to FIG. 2, the conventional bus switch includes a pre-charger 20 and a switch 22. The pre-charger 20 pre-charges the segment data bus SIO and SIOb to a desired reference voltage level in response to a bit line equalizing signal BLEQ. The switch 22 selectively couples the segment data bus SIO and SIOb with the local data bus LIO and LIOb in response to a bus switching signal IOSW.
The pre-charger 20 includes a first NMOS transistor T1 having a source/drain coupled with one line of the segment data bus SIO and a bit line pre-charge voltage end VBLP and receiving the bit line equalizing signal BLEQ as a gate input, a second NMOS transistor T2 having a source/drain coupled with the other line of the segment data bus SIOb and the bit line pre-charge voltage end VBLP and receiving the bit line equalizing signal BLEQ as a gate input, and a third NMOS transistor T3 having a source/drain coupled with the segment data bus SIO and SIOb and receiving the bit line equalizing signal BLEQ as a gate input.
Also, the switch 22 includes fourth and fifth transistors T4 and T5 which have a source/drain coupled with the segment data bus SIO and SIOb and the local data bus LIO and LIOb and receiving the bus switching signal IOSW as a gate input.
In a pre-charge mode when the bit line equalizing signal BLEQ is a logic high level, the pre-charger 20 equally pre-charges the segment data bus SIO and SIOb to the level of the bit line pre-charge voltage VBLP. Subsequently, in a read operation mode when the bit line equalizing signal BLEQ is enabled to a logic low level, a data is loaded on the segment data bus SIO and SIOb, and the data of the segment data bus SIO and SIOb is transferred to the local data bus LIO and LIOb through the switch 22 in response to the bus switching signal IOSW.
Here, the data is loaded on the segment data bus SIO and SIOb in a state that the segment data bus SIO and SIOb is pre-charged because an NMOS transistor (not shown), which receives the column selection signal Yi as a gate input, is turned on and the charges of the data are transferred to the segment data bus SIO and SIOb.
However, since the column selection signal Yi is a pulse signal activated to a logic high level for a short duration, the charge amount loaded on the segment data bus SIO and SIOb during such a short duration may not be sufficient to amplify the pre-charged voltage level of the segment data bus SIO and SIOb to a logic high/low level.
Therefore, when the bus switching signal IOSW is enabled to a logic high level, a delay occurs in driving the data of the segment data bus SIO and SIOb to the local data bus LIO and LIOb by the fourth and fifth NMOS transistors T4 and T5 of the switch 22. The delay may decrease the operation speed of the DRAM device.